Messages in this thread | | | From | Jisheng Zhang <> | Subject | [PATCH v3 0/2] riscv: improve nommu and timer-clint | Date | Wed, 10 Apr 2024 22:23:45 +0800 |
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As is known, the sophgo CV1800B contains so called little core, which is C906 w/o MMU, so I want to run nommu linux on it. This series is the result of the bring up. After this series, w/ proper dts, we can run nommu linux on milkv duo's little core.
First of all, patch1 removes the PAGE_OFFSET hardcoding by introducing DRAM_BASE Kconfig option.
Secondly, to use the T-HEAD C9xx clint in RISCV-M NOMMU env, we need to take care two points:
1.The mtimecmp in T-Head C9xx clint only supports 32bit read/write, implement such support.
2. As pointed out by commit ca7810aecdba ("lib: utils/timer: mtimer: add a quirk for lacking mtime register") of opensbi:
"T-Head developers surely have a different understanding of time CSR and CLINT's mtime register with SiFive ones, that they did not implement the mtime register at all -- as shown in openC906 source code, their time CSR value is just exposed at the top of their processor IP block and expects an external continous counter, which makes it not overrideable, and thus mtime register is not implemented, even not for reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS extended CSR, these systems still rely on the mtimecmp registers to generate timer interrupts. This makes it necessary to implement T-Head C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing reading mtime register and falls back to default code that reads time CSR."
So, we need to fall back to read time CSR instead of mtime register. Add riscv_csr_time_available static key for this purpose.
The second patch adds T-Head C9xxx clint support to timer-clint driver by taking care of above two points.
Since v2: - drop CONFIG_CLINT_USE_CSR_INSTEADOF_MTIME, instead we use runtime code patch to dynamically enable CSR TIME code path or MTIME code path.
Since v1: - fix c900_clint_timer_init_dt() defined but not used build warning - add option CONFIG_CLINT_USE_CSR_INSTEADOF_MTIME instead of removing mtime usage for all platforms, since not all platforms implement the time CSR in HW in M mode. - rebase on the timer-clint improvement series https://lore.kernel.org/linux-riscv/20240406111757.1597-1-jszhang@kernel.org/T/#t
Jisheng Zhang (2): riscv: nommu: remove PAGE_OFFSET hardcoding clocksource/drivers/timer-clint: Add T-Head C9xx clint
arch/riscv/Kconfig | 8 +++++- arch/riscv/include/asm/clint.h | 2 ++ arch/riscv/include/asm/timex.h | 18 +++++++++--- drivers/clocksource/timer-clint.c | 48 +++++++++++++++++++++++++++---- 4 files changed, 66 insertions(+), 10 deletions(-)
-- 2.43.0
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