Messages in this thread | | | Date | Thu, 1 Jun 2023 14:07:01 +0100 | From | Jonathan Cameron <> | Subject | Re: [PATCH v4 11/23] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport |
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On Tue, 23 May 2023 18:22:02 -0500 Terry Bowman <terry.bowman@amd.com> wrote:
> From: Robert Richter <rrichter@amd.com> > > Same as for ports, also store the downstream port's Component Register > mappings, use struct cxl_dport for that. > > Signed-off-by: Robert Richter <rrichter@amd.com> > Signed-off-by: Terry Bowman <terry.bowman@amd.com> Seems reasonable to me. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> --- > drivers/cxl/core/port.c | 11 +++++++++++ > drivers/cxl/cxl.h | 2 ++ > 2 files changed, 13 insertions(+) > > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index 34e929f1723b..db2ba0c886e2 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -708,6 +708,13 @@ static inline int cxl_port_setup_regs(struct cxl_port *port, > component_reg_phys); > } > > +static inline int cxl_dport_setup_regs(struct cxl_dport *dport, > + resource_size_t component_reg_phys) > +{ > + return cxl_setup_comp_regs(dport->dev, &dport->comp_map, > + component_reg_phys); > +} > + > static struct cxl_port *__devm_cxl_add_port(struct device *host, > struct device *uport, > resource_size_t component_reg_phys, > @@ -986,6 +993,10 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, > dport->port = port; > dport->rcrb.base = rcrb; > > + rc = cxl_dport_setup_regs(dport, component_reg_phys); > + if (rc && rc != -ENODEV) > + return ERR_PTR(rc); > + > cond_cxl_root_lock(port); > rc = add_dport(port, dport); > cond_cxl_root_unlock(port); > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index c76e1f84ba61..dc83c1d0396e 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -601,6 +601,7 @@ struct cxl_rcrb_info { > * struct cxl_dport - CXL downstream port > * @dev: PCI bridge or firmware device representing the downstream link > * @port: reference to cxl_port that contains this downstream port > + * @comp_map: component register capability mappings > * @port_id: unique hardware identifier for dport in decoder target list > * @component_reg_phys: downstream port component registers > * @rch: Indicate whether this dport was enumerated in RCH or VH mode > @@ -609,6 +610,7 @@ struct cxl_rcrb_info { > struct cxl_dport { > struct device *dev; > struct cxl_port *port; > + struct cxl_register_map comp_map; > int port_id; > resource_size_t component_reg_phys; > bool rch;
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