Messages in this thread | | | Date | Wed, 8 Mar 2023 14:33:58 -0600 | From | Rob Herring <> | Subject | Re: [PATCH] dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg |
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On Thu, 02 Mar 2023 16:52:55 +0100, Krzysztof Kozlowski wrote: > The description of second IO address is a bit confusing. It is supposed > to be the MCC range which contains the slew rate registers, not the slew > rate register base. The Linux driver then accesses slew rate register > with hard-coded offset (0xa000). > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > .../bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml | 2 +- > .../bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml | 2 +- > .../bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) >
Acked-by: Rob Herring <robh@kernel.org>
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