Messages in this thread | | | Date | Tue, 7 Mar 2023 14:39:59 +0100 | Subject | Re: [PATCH] dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg | From | Krzysztof Kozlowski <> |
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On 07/03/2023 14:32, Linus Walleij wrote: > On Thu, Mar 2, 2023 at 4:52 PM Krzysztof Kozlowski > <krzysztof.kozlowski@linaro.org> wrote: > >> The description of second IO address is a bit confusing. It is supposed >> to be the MCC range which contains the slew rate registers, not the slew >> rate register base. The Linux driver then accesses slew rate register >> with hard-coded offset (0xa000). >> >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > LGTM, is this something I should just apply or will you collect a larger > series of Qcom DT patches this time around as well?
Please grab it. I think I cleaned up Qualcomm pinctrl bindings from technical debt, thus no more work for me!
Best regards, Krzysztof
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