Messages in this thread | | | Date | Wed, 29 Mar 2023 15:21:09 +0200 | Subject | Re: [PATCH v3 08/17] arm64: dts: mediatek: add mmc support for mt8365 SoC | From | AngeloGioacchino Del Regno <> |
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Il 29/03/23 10:54, Alexandre Mergnat ha scritto: > There are three ports of MSDC (MMC and SD Controller), which are: > - MSDC0: EMMC5.1 > - MSDC1: SD3.0/SDIO3.0 > - MSDC2: SDIO3.0+ > > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> > --- > arch/arm64/boot/dts/mediatek/mt8365.dtsi | 39 ++++++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi > index 687011353f69..a67eeca28da5 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi > @@ -399,6 +399,45 @@ usb_host: usb@11200000 { > }; > }; > > + mmc0: mmc@11230000 { > + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; > + reg = <0 0x11230000 0 0x1000>, > + <0 0x11cd0000 0 0x1000>; > + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, > + <&infracfg CLK_IFR_MSDC0_HCLK>, > + <&infracfg CLK_IFR_MSDC0_SRC>; > + clock-names = "source", "hclk", "source_cg"; > + status = "disabled"; > + }; > + > + mmc1: mmc@11240000 { > + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; > + reg = <0 0x11240000 0 0x1000>, > + <0 0x11c90000 0 0x1000>; > + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, > + <&infracfg CLK_IFR_MSDC1_HCLK>, > + <&infracfg CLK_IFR_MSDC1_SRC>; > + clock-names = "source", "hclk", "source_cg"; > + status = "disabled"; > + }; > + > + mmc2: mmc@11250000 { > + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; > + reg = <0 0x11250000 0 0x1000>, > + <0 0x11c60000 0 0x1000>; > + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>, > + <&infracfg CLK_IFR_MSDC2_HCLK>, > + <&infracfg CLK_IFR_MSDC2_SRC>, > + <&infracfg CLK_IFR_MSDC2_BK>, > + <&infracfg CLK_IFR_AP_MSDC0>; > + clock-names = "source", "hclk", "source_cg", > + "bus_clk", "sys_cg";
clock-names for this do fit in one 90 columns line.
After compressing it,
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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