Messages in this thread Patch in this message | | | From | Benedikt Spranger <> | Subject | [PATCH 1/1] clk: socfpga: gate: Fix of by factor 2 for serial console | Date | Thu, 5 Oct 2023 11:59:27 +0200 |
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Commit 9607beb917df ("clk: socfpga: gate: Add a determine_rate hook") introduce a specific determine_rate hook. As a result the calculated clock for the serial IP is off by factor 2 after that i.e. if the system configures a baudrate of 115200 it is set physicaly to 57600.
Change the determine_rate hook to the reparent variant __clk_mux_determine_rate() to fix the issue.
Cc: stable@vger.kernel.org Fixes: 9607beb917df ("clk: socfpga: gate: Add a determine_rate hook") Signed-off-by: Benedikt Spranger <b.spranger@linutronix.de> --- drivers/clk/socfpga/clk-gate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index 8dd601bd8538..47500976f987 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -110,7 +110,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, static struct clk_ops gateclk_ops = { .recalc_rate = socfpga_clk_recalc_rate, - .determine_rate = clk_hw_determine_rate_no_reparent, + .determine_rate = __clk_mux_determine_rate, .get_parent = socfpga_clk_get_parent, .set_parent = socfpga_clk_set_parent, }; -- 2.42.0
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