Messages in this thread | | | Date | Thu, 5 Oct 2023 13:34:01 +0200 | From | Maxime Ripard <> | Subject | Re: [PATCH 1/1] clk: socfpga: gate: Fix of by factor 2 for serial console |
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Hi,
On Thu, Oct 05, 2023 at 11:59:27AM +0200, Benedikt Spranger wrote: > Commit 9607beb917df ("clk: socfpga: gate: Add a determine_rate hook") > introduce a specific determine_rate hook. As a result the calculated > clock for the serial IP is off by factor 2 after that i.e. if the system > configures a baudrate of 115200 it is set physicaly to 57600.
Where is that factor 2 coming from?
> Change the determine_rate hook to the reparent variant > __clk_mux_determine_rate() to fix the issue.
It's also not clear to me why that would fix anything. This patch should only make the old behaviour explicit, could you expand a bit on what happens?
Thanks! Maxime [unhandled content-type:application/pgp-signature] | |