| From | Geert Uytterhoeven <> | Date | Wed, 4 Oct 2023 14:57:39 +0200 | Subject | Re: [PATCH v2 15/28] pinctrl: renesas: rzg2l: adapt for different SD/PWPR register offsets |
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On Fri, Sep 29, 2023 at 7:39 AM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > SD, PWPR power registers have different offsets b/w RZ/G2L and RZ/G3S. > Commit adds a per SoC configuration data structure that is initialized with > proper register offset for individual SoCs. The struct rzg2l_hwcfg will be > further extended in next commits. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > > Changes in v2: > - collected tags
Thanks, will queue in renesas-pinctrl-for-v6.7.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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