Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Tue, 3 Oct 2023 17:14:51 +0200 | Subject | Re: [PATCH v2 02/28] clk: renesas: rzg2l: wait for status bit of SD mux before continuing |
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On Fri, Sep 29, 2023 at 7:39 AM Claudiu <claudiu.beznea@tuxon.dev> wrote: > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > > Hardware user manual of RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf, > chapter 7.4.7 Procedure for Switching Clocks by the Dynamic Switching > Frequency Selectors) specifies that we need to check CPG_PL2SDHI_DSEL for > SD clock switching status. > > Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support") > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> > --- > > Changes in v2: > - initialized msk
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v6.7.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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