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Subject[PATCH 0/7] irqchip/renesas-rzg2l: add support for RZ/G3S SoC
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From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Hi,

Series adds support for IA55 available on RZ/G3S SoC.
Patches are split as follows:
- 1/7 updates documentation
- 2/7 adds IA55 clock
- 3/7 minor cleanup on the way TITSR fields are populated
- 4/7 implement restriction described in HW manual for ISCR register
- 5/7 adds support for suspend to RAM
- 6/7 minor cleanup that replaces spaces with tabs on macro definition
- 7/7 adds IA55 device tree node

Thank you,
Claudiu Beznea

Claudiu Beznea (7):
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: document RZ/G3S
clk: renesas: r9a08g045: add IA55 pclk and its reset
irqchip/renesas-rzg2l: add macros to retrieve TITSR index and
associated selector
irqchip/renesas-rzg2l: implement restriction when writing ISCR
register
irqchip/renesas-rzg2l: cache registers on suspend/resume
irqchip/renesas-rzg2l: use tabs instead of spaces
arm64: dts: renesas: r9108g045: add irqc

.../renesas,rzg2l-irqc.yaml | 5 +-
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 68 +++++++++++
drivers/clk/renesas/r9a08g045-cpg.c | 3 +
drivers/irqchip/irq-renesas-rzg2l.c | 111 ++++++++++++------
4 files changed, 152 insertions(+), 35 deletions(-)

--
2.39.2

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