Messages in this thread | | | From | "Lad, Prabhakar" <> | Date | Fri, 27 Jan 2023 20:44:27 +0000 | Subject | Re: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node |
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Hi Biju,
Thank you for the review.
On Fri, Jan 27, 2023 at 6:38 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > Hi Prabhakar, > > Thanks for the patch. > > > Subject: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Enable the performance monitor unit for the Cortex-A55 cores on the RZ/G2L > > (r9a07g044) SoC. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > index 80b2332798d9..ff9bdc03a3ed 100644 > > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > @@ -161,6 +161,11 @@ opp-50000000 { > > }; > > }; > > > > + pmu_a55 { > > + compatible = "arm,cortex-a55-pmu"; > > + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; > > Just a question, Is it tested? Yes this was tested with perf test (https://pastebin.com/dkckcYHr)
> timer node[1] defines irq type as LOW, here it is high. You are right looking at the RZG2L_InterruptMapping_rev01.xlsx this should be LOW. (I followed the SPI IRQS where all the LEVEL interrupts are HIGH)
> Also do we need to define (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW) as it has 2 cores?? > No this is not required for example here [0] where it has 6 cores.
[0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/r8a779f0.dtsi?h=v6.2-rc5#n203
Cheers, Prabhakar
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