Messages in this thread | | | From | Biju Das <> | Subject | RE: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node | Date | Fri, 27 Jan 2023 18:38:05 +0000 |
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Hi Prabhakar,
Thanks for the patch.
> Subject: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Enable the performance monitor unit for the Cortex-A55 cores on the RZ/G2L > (r9a07g044) SoC. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > index 80b2332798d9..ff9bdc03a3ed 100644 > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > @@ -161,6 +161,11 @@ opp-50000000 { > }; > }; > > + pmu_a55 { > + compatible = "arm,cortex-a55-pmu"; > + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
Just a question, Is it tested? timer node[1] defines irq type as LOW, here it is high. Also do we need to define (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW) as it has 2 cores??
[1] timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; };
Cheers, Biju
> + }; > + > psci { > compatible = "arm,psci-1.0", "arm,psci-0.2"; > method = "smc"; > -- > 2.25.1
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