Messages in this thread Patch in this message | | | From | Konrad Dybcio <> | Subject | [PATCH 1/6] clk: qcom: gcc-sdm660: Fix hmss_gpll0_clk_src parent_map | Date | Sat, 20 Feb 2021 16:56:12 +0100 |
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The correct one is gcc_parent_map_xo_gpll0.
Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660") Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> --- drivers/clk/qcom/gcc-sdm660.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c index 6394257ca8c0..597800ce1bdf 100644 --- a/drivers/clk/qcom/gcc-sdm660.c +++ b/drivers/clk/qcom/gcc-sdm660.c @@ -626,12 +626,12 @@ static struct clk_rcg2 hmss_gpll0_clk_src = { .cmd_rcgr = 0x4805c, .mnd_width = 0, .hid_width = 5, - .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, + .parent_map = gcc_parent_map_xo_gpll0, .freq_tbl = ftbl_hmss_gpll0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_gpll0_clk_src", - .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .parent_names = gcc_parent_names_xo_gpll0, + .num_parents = 2, .ops = &clk_rcg2_ops, }, }; -- 2.30.1
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