Messages in this thread Patch in this message | ![/](/images/icornerl.gif) | | From | Lad Prabhakar <> | Subject | [PATCH v2] clk: renesas: r8a7742-cpg-mssr: Add clk entry for VSPR | Date | Mon, 31 Aug 2020 19:03:12 +0100 |
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Add clock entry 130 for VSPR (VSP for Resizing) module, so that this module can be used on R8A7742 (RZ/G1H) SoC.
Alongside rename clock entry "vsp1-sy" to "vsps" (VSP Standard), so that VSP1 clock names are in sync.
Note: The entry for VSPR clock was accidentally dropped from RZ/G manual when all the information related to RT were removed.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> --- v1->v2 * Alongside renamed "vsp1-sy" to "vsps" * Updated commit message --- drivers/clk/renesas/r8a7742-cpg-mssr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r8a7742-cpg-mssr.c b/drivers/clk/renesas/r8a7742-cpg-mssr.c index e919828668a4..e541489bd1cd 100644 --- a/drivers/clk/renesas/r8a7742-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7742-cpg-mssr.c @@ -97,7 +97,8 @@ static const struct mssr_mod_clk r8a7742_mod_clks[] __initconst = { DEF_MOD("tmu0", 125, R8A7742_CLK_CP), DEF_MOD("vsp1du1", 127, R8A7742_CLK_ZS), DEF_MOD("vsp1du0", 128, R8A7742_CLK_ZS), - DEF_MOD("vsp1-sy", 131, R8A7742_CLK_ZS), + DEF_MOD("vspr", 130, R8A7742_CLK_ZS), + DEF_MOD("vsps", 131, R8A7742_CLK_ZS), DEF_MOD("scifa2", 202, R8A7742_CLK_MP), DEF_MOD("scifa1", 203, R8A7742_CLK_MP), DEF_MOD("scifa0", 204, R8A7742_CLK_MP), -- 2.17.1
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