Messages in this thread Patch in this message | | | From | Qiu Wenbo <> | Subject | [PATCH] riscv: Setup exception vector for K210 properly | Date | Tue, 11 Aug 2020 14:36:56 +0800 |
| |
Exception vector is missing on nommu platform and it is a big issue. This patch is tested in Sipeed MAIX Bit Dev Board.
Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early") Signed-off-by: Qiu Wenbo <qiuwenbo@phytium.com.cn> --- arch/riscv/kernel/smpboot.c | 1 + arch/riscv/kernel/traps.c | 11 ++++++++++- 2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 356825a57551..23cde0ceb39d 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -154,6 +154,7 @@ asmlinkage __visible void smp_callin(void) mmgrab(mm); current->active_mm = mm; + trap_init(); notify_cpu_starting(curr_cpuid); update_siblings_masks(curr_cpuid); set_cpu_online(curr_cpuid, 1); diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index ad14f4466d92..a390239818ae 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -174,7 +174,16 @@ int is_valid_bugaddr(unsigned long pc) } #endif /* CONFIG_GENERIC_BUG */ -/* stvec & scratch is already set from head.S */ +/* stvec & scratch is already set from head.S when mmu is enabled */ void trap_init(void) { +#ifndef CONFIG_MMU + /* + * Set sup0 scratch register to 0, indicating to exception vector + * that we are presently executing in the kernel + */ + csr_write(CSR_SCRATCH, 0); + /* Set the exception vector address */ + csr_write(CSR_TVEC, &handle_exception); +#endif } -- 2.28.0
| |