Messages in this thread | | | From | Bharat Kumar Gogada <> | Subject | [PATCH v9 0/2] Adding support for Versal CPM as Root Port driver | Date | Tue, 16 Jun 2020 18:26:52 +0530 |
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- Adding support for Versal CPM as Root port. - The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrated block for CPM along with the integrated bridge can function as PCIe Root Port. - Versal CPM uses GICv3 ITS feature for assigning MSI/MSI-X vectors and handling MSI/MSI-X interrupts. - Bridge error and legacy interrupts in Versal CPM are handled using Versal CPM specific interrupt line.
Changes for v9: - Removed interrupt enablement outside irqchip flow as suggested by Marc. - Removed using WARN_ON in if statement.
Bharat Kumar Gogada (2): PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port PCI: xilinx-cpm: Add Versal CPM Root Port driver
.../devicetree/bindings/pci/xilinx-versal-cpm.yaml | 99 ++++ drivers/pci/controller/Kconfig | 8 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-xilinx-cpm.c | 615 +++++++++++++++++++++ 4 files changed, 723 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml create mode 100644 drivers/pci/controller/pcie-xilinx-cpm.c
-- 2.7.4
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