Messages in this thread | | | Date | Thu, 8 Aug 2019 10:08:41 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH V2 01/10] x86/CPU: Expose if cache is inclusive of lower level caches |
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On Tue, Aug 06, 2019 at 02:16:10PM -0700, Reinette Chatre wrote: > > I'd leave it to tglx to say how we should mirror cache inclusivity in > > cpuinfo_x86: whether a synthetic X86_FEATURE bit or cache the respective > > CPUID words which state whether L2/L3 is inclusive... > > Thank you very much. I appreciate your guidance here.
Ok, tglx and I talked it over a bit on IRC: so your 1/10 patch is pretty close - just leave out the generic struct cacheinfo bits and put the cache inclusivity property in a static variable there. It will be a single bit of information only anyway, as this is system-wide and we can always move it to generic code when some other arch wants it too.
Thx.
-- Regards/Gruss, Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
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