Messages in this thread | | | Date | Tue, 6 Aug 2019 22:40:54 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH V2 01/10] x86/CPU: Expose if cache is inclusive of lower level caches |
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On Tue, Aug 06, 2019 at 01:22:22PM -0700, Reinette Chatre wrote: > ... because some platforms differ in which SKUs support cache > pseudo-locking. On these platforms only the SKUs with inclusive cache > support cache pseudo-locking, thus the additional check.
Ok, so it sounds to me like that check in get_prefetch_disable_bits() should be extended (and maybe renamed) to check for cache inclusivity too, in order to know which platforms support cache pseudo-locking. I'd leave it to tglx to say how we should mirror cache inclusivity in cpuinfo_x86: whether a synthetic X86_FEATURE bit or cache the respective CPUID words which state whether L2/L3 is inclusive...
Thx.
-- Regards/Gruss, Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
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