Messages in this thread Patch in this message | | | From | Maxime Ripard <> | Subject | [PATCH] ARM: dts: sun8i: a23/a33: Add R_I2C Controller | Date | Mon, 18 Mar 2019 13:56:13 +0100 |
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The A23 and A33 both have an I2C controller in the ARISC domain, that share the same pins with the RSB bus.
Even if it's an unusual configuration, that device can be used to drive the PMIC, so let's use it.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 43fe215e83ea..2eed7a2d7d7e 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -799,6 +799,20 @@ status = "disabled"; }; + r_i2c: i2c@1f02400 { + compatible = "allwinner,sun8i-a23-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01f02400 0x400>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c_pins>; + clocks = <&apb0_gates 6>; + resets = <&apb0_rst 6>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-a23-r-pinctrl"; reg = <0x01f02c00 0x400>; @@ -811,6 +825,12 @@ #interrupt-cells = <3>; #gpio-cells = <3>; + r_i2c_pins: r-i2c-pins { + pins = "PL0", "PL1"; + function = "s_i2c"; + bias-pull-up; + }; + r_rsb_pins: r-rsb-pins { pins = "PL0", "PL1"; function = "s_rsb"; -- 2.20.1
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