Messages in this thread | | | From | Lei Wen <> | Date | Sat, 8 Dec 2018 20:04:50 +0800 | Subject | Coresight etmv4 enable over 32bit kernel |
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Hi Mathieu,
I am enabling etmv4 coresight over one Cortex-A7 soc, using 32bit kernel. And I am following [1] to do experiment regarding the addr_range feature. The default addr_range is set as _stext~_etext, and it works fine with etb as sink, and etm as source. I could see there are valid kernel addresses using OpenCSD.
But while I try to store one small range of address pair, which contain only one kernel function. It doesn't behavior like what said in [1], the write pointer would grows rapidly with the read pointer. And I dump the etb buffer and parse it with openCSD, finding that there is no I_ASYNC packet in the dump and is fulled with I_NOT_SYNC.
So my question is why ETB continue to grow when there is no trigger at all? Is it normal? I could provide more info if you need it.
[1]: https://wiki.linaro.org/WorklingGroups/Kernel/Coresight/traceDecodingWithDS5
Thanks, Lei
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