Messages in this thread Patch in this message | | | From | Jernej Skrabec <> | Subject | [PATCH] clk: sunxi-ng: a64: Allow parent change for VE clock | Date | Sat, 8 Dec 2018 19:02:22 +0100 |
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Cedrus driver wants to set VE clock higher than it's possible without changing parent rate.
Allow changing parent rate for VE clock, so clock rate can be set freely.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> --- drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index 5f80eb018014..1e2cd37cf0b8 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -554,7 +554,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, 0x134, 0, 5, 8, 3, BIT(15), 0); static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", - 0x13c, 16, 3, BIT(31), 0); + 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", 0x140, BIT(31), CLK_SET_RATE_PARENT); -- 2.19.2
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