Messages in this thread Patch in this message | | | From | "Natarajan, Janakarajan" <> | Subject | [PATCH] x86/cpufeatures: Add WBNOINVD feature definition | Date | Wed, 7 Nov 2018 20:59:07 +0000 |
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Add a new cpufeature definition for the WBNOINVD instruction.
The WBNOINVD instruction writes all modified line in all levels of cache associated with a processor to main memory while retaining the cached values.
Both AMD and Intel support this instruction.
Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 28c4a50..39a48f0 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -281,6 +281,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ +#define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */ #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */ -- 2.7.4
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