Messages in this thread | | | Date | Mon, 18 Sep 2017 16:34:08 -0700 (PDT) | Subject | Re: [PATCH net] net: phy: Fix mask value write on gmii2rgmii converter speed register | From | David Miller <> |
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From: Fahad Kunnathadi <fahad.kunnathadi@dexceldesigns.com> Date: Fri, 15 Sep 2017 12:01:58 +0530
> To clear Speed Selection in MDIO control register(0x10), > ie, clear bits 6 and 13 to zero while keeping other bits same. > Before AND operation,The Mask value has to be perform with bitwise NOT > operation (ie, ~ operator) > > This patch clears current speed selection before writing the > new speed settings to gmii2rgmii converter > > Fixes: f411a6160bd4 ("net: phy: Add gmiitorgmii converter support") > > Signed-off-by: Fahad Kunnathadi <fahad.kunnathadi@dexceldesigns.com> > Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Applied and queued up for -stable, thanks.
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