Messages in this thread | | | From | Heiko Stuebner <> | Subject | Re: [RESEND PATCH v2 1/5] clk: rockchip: add more mux parameters for new pll sources | Date | Wed, 09 Mar 2016 02:12:31 +0100 |
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Am Dienstag, 1. März 2016, 18:14:31 schrieb Xing Zheng: > Thers are only two parent PLLs that APLL and GPLL for core on the > previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed > GPLL as alternate parent when core is switching freq. > > Since RK3399 big.LITTLE architecture, we need to select and adapt > more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources. > > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
note to self: looks good to go
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