Messages in this thread | | | Date | Mon, 14 Sep 2015 14:11:56 +0200 | From | Peter Zijlstra <> | Subject | Re: [RFC 3/5] powerpc: atomic: implement atomic{,64}_{add,sub}_return_* variants |
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On Mon, Sep 14, 2015 at 02:01:53PM +0200, Peter Zijlstra wrote: > The scenario is: > > CPU0 CPU1 > > unlock(x) > smp_store_release(&x->lock, 0); > > unlock(y) > smp_store_release(&next->lock, 1); /* next == &y */ > > lock(y) > while (!(smp_load_acquire(&y->lock)) > cpu_relax(); > > > Where the lock does _NOT_ issue a store to acquire the lock at all. Now > I don't think any of our current primitives manage this, so we should be > good, but it might just be possible.
So with a bit more through this seems fundamentally impossible, you always needs some stores in a lock() implementation, the above for instance needs to queue itself, otherwise CPU0 will not be able to find it etc..
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