Messages in this thread | | | Date | Fri, 28 Aug 2015 20:06:14 +0800 | From | Boqun Feng <> | Subject | Re: [RFC 3/5] powerpc: atomic: implement atomic{,64}_{add,sub}_return_* variants |
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Hi Peter,
On Fri, Aug 28, 2015 at 12:48:54PM +0200, Peter Zijlstra wrote: > On Fri, Aug 28, 2015 at 10:48:17AM +0800, Boqun Feng wrote: > > +/* > > + * Since {add,sub}_return_relaxed and xchg_relaxed are implemented with > > + * a "bne-" instruction at the end, so an isync is enough as a acquire barrier > > + * on the platform without lwsync. > > + */ > > +#ifdef CONFIG_SMP > > +#define smp_acquire_barrier__after_atomic() \ > > + __asm__ __volatile__(PPC_ACQUIRE_BARRIER : : : "memory") > > +#else > > +#define smp_acquire_barrier__after_atomic() barrier() > > +#endif > > +#define arch_atomic_op_acquire(op, args...) \ > > +({ \ > > + typeof(op##_relaxed(args)) __ret = op##_relaxed(args); \ > > + smp_acquire_barrier__after_atomic(); \ > > + __ret; \ > > +}) > > + > > +#define arch_atomic_op_release(op, args...) \ > > +({ \ > > + smp_lwsync(); \ > > + op##_relaxed(args); \ > > +}) > > Urgh, so this is RCpc. We were trying to get rid of that if possible. > Lets wait until that's settled before introducing more of it. > > lkml.kernel.org/r/20150820155604.GB24100@arm.com
OK, get it. Thanks.
So I'm not going to introduce these arch specific macros, I think what I need to implement are just _relaxed variants and cmpxchg_acquire.
Regards, Boqun
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