Messages in this thread | | | Date | Wed, 25 Feb 2015 19:20:32 +0100 | From | Andi Kleen <> | Subject | Re: [PATCH 1/3] x86: Move msr accesses out of line |
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> Still, I wondered, so I ran me a little test. Note that I used a > serializing instruction (LOCK XCHG) because WRMSR is too.
WRMSR has a lot of uops internally unlike LOCK XCHG, so I expect it will mostly overlap with what it does. I'll run some benchmarks on this today.
Also we do quite a few RDMSRs, which are not necessarily serializing.
> I see a ~14 cycle difference between the inline and noinline version. > > If I substitute the LOCK XCHG with XADD, I get to 1,5 cycles in > difference, so clearly there is some magic happening, but serializing > instructions wreck it. > > Anybody can explain how such RSP deps get magiced away?
On Intel Core (since Yonah), the CPU frontend has a special stack tracker that avoids these dependencies.
See 2.3.2.5 in the optimization manual
Also BTW just from tracing MSRs there is a lot of optimization potential. Will send some patches later.
-Andi
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