Messages in this thread | | | Date | Fri, 2 Mar 2012 16:25:06 +0100 | From | Ingo Molnar <> | Subject | Re: change last level cache alignment on x86? |
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* Alex Shi <alex.shi@intel.com> wrote:
> So, with defconfig on x86_64, I saw much changes in System.map: > before patched after patched > ... > 000000000000b000 d tlb_vector_| 000000000000b000 d tlb_vector > 000000000000b080 d cpu_loops_p| 000000000000b040 d cpu_loops_ > ...
Ok, mind sending a patch, changelogged, with a SOB?
Thanks,
Ingo
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