Messages in this thread | | | Subject | Re: [PATCH 3/4] perf, x86: Add Intel SandyBridge pricise store support | From | Peter Zijlstra <> | Date | Mon, 11 Jul 2011 10:32:28 +0200 |
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On Mon, 2011-07-04 at 08:02 +0000, Lin Ming wrote: > Implements Intel memory store event for SandyBridge. > > $ perf mem -t store record make -j8
I was just looking through the Intel SDM, and stumbled upon:
C0H 01H INST_RETIRED.PREC_DIST
Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution PMC1 only; Must quiesce other PMCs. ^^^^^^^^^^^^^^^^^^^^^^^^
WTF!? Are they real? The implementation as provided by you doesn't do that (quite understandably), but please check with the hardware folks.
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