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SubjectRe: [PATCH 1/4] perf: Add memory load/store events generic code
On Mon, Jul 04, 2011 at 01:16:32PM +0200, Peter Zijlstra wrote:
> On Mon, 2011-07-04 at 08:02 +0000, Lin Ming wrote:
> > +#define MEM_STORE_DCU_HIT (1ULL << 0)
>
> I'm pretty sure that's not Dublin City University, but what is it?
> Data-Cache-Unit?

Yes

> what does that mean, L1/L2 or also L3?

DCU is L1D

(L2 would be MLC, L3 is LLC in Intelnese)

> > +#define MEM_STORE_STLB_HIT (1ULL << 1)
>
> What's an sTLB? I know iTLB and dTLB's but sTLBs I've not heard of yet.

Second Level TLB (for both i and d)

-Andi
--
ak@linux.intel.com -- Speaking for myself only.


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