Messages in this thread | | | Date | Mon, 24 Oct 2011 13:06:08 +0100 | Subject | Re: [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio | From | "Girdwood, Liam" <> |
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On 24 October 2011 04:32, Axel Lin <axel.lin@gmail.com> wrote: > According to the datasheet: > The PLL Output clock division ratio is controlled by BIT[5:4] of > WM8940_GPIO register(08h). > Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong. > > Signed-off-by: Axel Lin <axel.lin@gmail.com> > --- > sound/soc/codecs/wm8940.c | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c > index a4abfdf..3cc3bce 100644 > --- a/sound/soc/codecs/wm8940.c > +++ b/sound/soc/codecs/wm8940.c > @@ -627,8 +627,8 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai, > ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 5)); > break; > case WM8940_OPCLKDIV: > - reg = snd_soc_read(codec, WM8940_ADDCNTRL) & 0xFFCF; > - ret = snd_soc_write(codec, WM8940_ADDCNTRL, reg | (div << 4)); > + reg = snd_soc_read(codec, WM8940_GPIO) & 0xFFCF; > + ret = snd_soc_write(codec, WM8940_GPIO, reg | (div << 4)); > break; > } > return ret; > --
Acked-by: Liam Girdwood <lrg@ti.com> -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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