Messages in this thread Patch in this message | | | Subject | Re: [PATCH 3/9] oprofile, perf, x86: introduce new functions to reserve perfctrs by index | From | Andi Kleen <> | Date | Sat, 20 Mar 2010 06:45:44 +0100 |
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Robert Richter <robert.richter@amd.com> writes:
> Current perfctr reservation code allocates single pmu msrs. The msr > addresses may differ depending on the model and offset calculation is > necessary. This can be easier implemented by reserving a counter by > its index only.
Sorry reviewing old patch. This doesn't work for the fixed counters on intel, which don't have a index (or rather they have a separate number space)
I had a old patch to fix the reservation for them (and a matching patch to perf to use it).
How to resolve this?
-Andi
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--- arch/x86/kernel/cpu/perfctr-watchdog.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
Index: linux-2.6.32-ak/arch/x86/kernel/cpu/perfctr-watchdog.c =================================================================== --- linux-2.6.32-ak.orig/arch/x86/kernel/cpu/perfctr-watchdog.c +++ linux-2.6.32-ak/arch/x86/kernel/cpu/perfctr-watchdog.c @@ -70,9 +70,13 @@ static inline unsigned int nmi_perfctr_m case X86_VENDOR_AMD: return msr - MSR_K7_PERFCTR0; case X86_VENDOR_INTEL: - if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) + if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { + if (msr >= MSR_CORE_PERF_FIXED_CTR0 && + msr < MSR_CORE_PERF_FIXED_CTR0 + 8) + return NMI_MAX_COUNTER_BITS - + (msr - MSR_CORE_PERF_FIXED_CTR0); return msr - MSR_ARCH_PERFMON_PERFCTR0; - + } switch (boot_cpu_data.x86) { case 6: return msr - MSR_P6_PERFCTR0;
-- ak@linux.intel.com -- Speaking for myself only.
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