Messages in this thread | | | Date | 3 Feb 2010 18:56:44 -0500 | From | "George Spelvin" <> | Subject | Re: USB mass storage and ARM cache coherency |
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> Apart from that, flush_dcache_page() doesn't have any data flow > information. Optimisations could be done on ARM if we know that the > kernel only intends to read from a page (no flushing necessary with a > non-aliasing D-cache).
Already done in flush_dcache_page(). If possible (uniprocessor), it just flags the page as PG_dcache_dirty, and defers the actual flush operation until it's mapped somewhere else (either a virtual alias or executable).
See Documentation/cachetlb.txt. (Really, all PIO drivers should be calling flush_dcache_page.)
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