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Subject[RFC PATCH] C2 could be mapped to C3 so need a flush cache
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Hi there,

I came across acpi_idle_enter_simple, noticed it looks like a bug if
we don't flush cache for C2.
Because some platforms just map C2 to C3.

Please review. If make sense, please apply.

Ps. The patch is enclosed in attachment. The inlined one
is c&p of it for reading.


Thanks,
Luming

Signed-off-by: Yu Luming <luming.yu@intel.com>

processor_idle.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index 0efa59e..4fa9582 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -893,7 +893,7 @@ static int acpi_idle_enter_simple(struct
cpuidle_device *dev,
*/
lapic_timer_state_broadcast(pr, cx, 1);

- if (cx->type == ACPI_STATE_C3)
+ if (cx->type == ACPI_STATE_C3 || cx->type == ACPI_STATE_C2)
ACPI_FLUSH_CPU_CACHE();

kt1 = ktime_get_real();[unhandled content-type:application/octet-stream]
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