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Subject[PATCH 0/14] Page table handling updates for AMD-IOMMU (AMD-Vi)

this series of patches enhance the page table handling code for
AMD-IOMMU (AMD-Vi). With these patches the page table handling code is
able to map a full 64 bit device address space. The old limit was a 39
bit address space.
This series also contains initial patches for upcoming large page
support in the AMD-Vi driver. Full large page support requires changes
to the IOMMU-API which are not part of this patch set.



arch/x86/include/asm/amd_iommu_types.h | 38 +++---
arch/x86/kernel/amd_iommu.c | 242 ++++++++++++++++++++------------
2 files changed, 170 insertions(+), 110 deletions(-)


Joerg Roedel (14):
x86/amd-iommu: Make fetch_pte aware of dynamic mapping levels
x86/amd-iommu: Use fetch_pte in iommu_unmap_page
x86/amd-iommu: Use fetch_pte in amd_iommu_iova_to_phys
x86/amd-iommu: Add a gneric version of amd_iommu_flush_all_devices
x86/amd-iommu: Introduce set_dte_entry function
x86/amd-iommu: Flush domains if address space size was increased
x86/amd-iommu: Introduce increase_address_space function
x86/amd-iommu: Change alloc_pte to support 64 bit address space
x86/amd-iommu: Remove last usages of IOMMU_PTE_L0_INDEX
x86/amd-iommu: Remove bus_addr check in iommu_map_page
x86/amd-iommu: Use 2-level page tables for dma_ops domains
x86/amd-iommu: Remove old page table handling macros
x86/amd-iommu: Support higher level PTEs in iommu_page_unmap
x86/amd-iommu: Change iommu_map_page to support multiple page sizes

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