Messages in this thread | | | From | "Michael S. Zick" <> | Subject | Re: Linux 2.6.30-rc8 [also: VIA Support] | Date | Thu, 4 Jun 2009 16:01:30 -0500 |
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On Thu June 4 2009, Dave Jones wrote: > On Thu, Jun 04, 2009 at 01:12:43PM -0500, Michael S. Zick wrote: > > On Thu June 4 2009, Harald Welte wrote: > > > On Thu, Jun 04, 2009 at 11:21:28AM -0500, Michael S. Zick wrote: > > > > > > > That is one of my pending questions - - > > > > (It is included as a comment at the appropriate point in my patchset.) > > > > > > > > The VIA processors have MCR's not MTRR's - - > > > > > > AFAIK, that was true for processors like the Winhcip / C6, i.e. earlier than > > > the C3. The C3, C7 and later support 8 intel-style MTRR's. > > > > > > > Super! A specific breakage! > > > > The c7 setup code is re-using the c6 setup code (MCR's) - - > > Will "if 0" out the appropriate parts and arrange for the MTRR setup. > > It's not touching the MCRs. C7's are family 6. The MCR code is only > called for family 5. (Winchips) Look at the switch statement > in init_centaur() >
Yup, mis-read that one - -
case 6: init_c3(c); break;
= = = =
But while your here, what is your opinion on this one, in: int __init pcibios_init(void)
- - - - - pci_cache_line_size = 32 >> 2; if (c->x86 >= 6 && (c->x86_vendor == X86_VENDOR_AMD) || (c->x86_vendor == X86_VENDOR_CENTAUR)) pci_cache_line_size = 64 >> 2; /* K7 & K8 and VIA C7-M */ else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL) pci_cache_line_size = 128 >> 2; /* P4 */
Mike
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