Messages in this thread Patch in this message | | | From | Paul Walmsley <> | Subject | [PATCH 01/10] OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize | Date | Tue, 26 May 2009 16:12:28 -0600 |
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The original CDP kernel that this code comes from waited for 0x800 loops after switching the CORE DPLL M2 divider. This does not appear to be necessary.
Signed-off-by: Paul Walmsley <paul@pwsan.com> --- arch/arm/mach-omap2/sram34xx.S | 3 --- 1 files changed, 0 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index c080c82..84781a6 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -102,9 +102,6 @@ configure_core_dpll: orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val str r12, [r11] ldr r12, [r11] @ posted-write barrier for CM - mov r12, #0x800 @ wait for the clock to stabilise - cmp r3, #2 - bne wait_clk_stable bx lr wait_clk_stable: subs r12, r12, #1
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