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    Subject[PATCH 08/10] OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLL
    Date
    Correspondence with the TI OMAP hardware team indicates that
    SDRC_DLLA_CTRL.FIXEDDELAY should be initialized to 0x0f. This number
    was apparently derived from process validation. This is only used
    when the SDRC DLL is unlocked (e.g., SDRC clock frequency less than
    83MHz).

    Signed-off-by: Paul Walmsley <paul@pwsan.com>
    ---
    arch/arm/mach-omap2/sram34xx.S | 12 ++++++++++++
    1 files changed, 12 insertions(+), 0 deletions(-)

    diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
    index 487fa86..f41f8d9 100644
    --- a/arch/arm/mach-omap2/sram34xx.S
    +++ b/arch/arm/mach-omap2/sram34xx.S
    @@ -41,8 +41,18 @@
    #define SDRC_UNLOCK_DLL 0x1

    /* SDRC_DLLA_CTRL bit settings */
    +#define FIXEDDELAY_SHIFT 24
    +#define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT)
    #define DLLIDLE_MASK 0x4

    +/*
    + * SDRC_DLLA_CTRL default values: TI hardware team indicates that
    + * FIXEDDELAY should be initialized to 0xf. This apparently was
    + * empirically determined during process testing, so no derivation
    + * was provided.
    + */
    +#define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT)
    +
    /* SDRC_DLLA_STATUS bit settings */
    #define LOCKSTATUS_MASK 0x4

    @@ -103,6 +113,8 @@ return_to_sdram:
    unlock_dll:
    ldr r11, omap3_sdrc_dlla_ctrl
    ldr r12, [r11]
    + and r12, r12, #FIXEDDELAY_MASK
    + orr r12, r12, #FIXEDDELAY_DEFAULT
    orr r12, r12, #DLLIDLE_MASK
    str r12, [r11] @ (no OCP barrier needed)
    bx lr



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