Messages in this thread | | | Date | Sat, 28 Jun 2008 10:14:31 +0100 | From | Alan Cox <> | Subject | Re: [PATCH v2 -rt] ide: workaround buggy hardware issues with preemptable hardirqs |
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> But some hardware (namely ULi M5228 in the ULi M1575 "Super South Brige") > behaves in a strange way: it asserts interrupts as edge sensitive. And > because preemptable IRQ handler disables PIC's interrupt, PIC will likely > miss it.
You mean "I've programmed the hardware wrong"
If your M5228 is in native mode it should be generating a level trigger, providing you've programmed it in full that way. If you have it in legacy mode then it honours IDEIRT and you want the relevant PIC/APIC input set to level.
How to program an IDE controller out of legacy mode is a public open standard document.
> It would be great to re-configure the ULi bridge or ULi IDE controller > to behave sanely, but no one knows how or if this is possible at all > (no available specifications).
You need an NDA with ULi for the documentation or I suspect you can program the APIC or EISA level registers to match assuming its a PCI like bridge.
> So.. to workaround the issue IDE interrupt handler should re-check for > any pending IRQs. This isn't bulletproof solution, but it works and this > is the best one we can do.
That really does not belong in a mainstream tree.
Alan
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