Messages in this thread | | | Date | Wed, 16 Aug 2006 18:24:21 -0500 | Subject | Re: [PATCH 1/2]: powerpc/cell spidernet bottom half | From | (Linas Vepstas) |
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On Wed, Aug 16, 2006 at 02:32:03PM -0700, David Miller wrote: > > The best schemes seem to be to interrupt mitigate using a combination > of time and number of TX entries pending to be purged. This is what > most gigabit chips seem to offer.
I seem to be having a multi-hour delay for email delivery, so maybe we've crossed emails.
A "low watermark interrupt" is an interrupt that is generated when some queue is "almost empty". This last set of patches implement this for the TX queue. The interrupt pops when 3/4ths of the packets in the queue have been processed. Playing with ths setting (3/4ths or some other number) seemed to make little difference.
> On Tigon3, for example, we tell the chip to interrupt if either 53 > frames or 150usecs have passed since the first TX packet has become > available for reclaim.
The nature of a low-watermark interrupt is that it NEVER pops, as long as the kernel keeps putting more stuff into the queue, so as to keep the queue at least 1/4'th full. I don't know how to mitigate interrupts more than that.
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