Messages in this thread | | | Date | Thu, 3 Mar 2005 09:43:37 -0800 | From | "David S. Miller" <> | Subject | Re: Page fault scalability patch V18: Drop first acquisition of ptl |
| |
On Thu, 03 Mar 2005 17:30:28 +1100 Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
> On Fri, 2005-03-04 at 04:19 +1100, Nick Piggin wrote: > > > You don't want to do that for all architectures, as I said earlier. > > eg. i386 can concurrently set the dirty bit with the MMU (which won't > > honour the lock). > > > > So you then need an atomic lock, atomic pte operations, and atomic > > unlock where previously you had only the atomic pte operation. This is > > disastrous for performance. > > Of course, but I was answering to David about sparc64 which uses > software TLB load :)
Right.
The current situation on sparc64 is that the tlb miss handler is ~10 cycles.
Like I said, I can use this thing if it just increases access, without modifying the TLB miss handler at all.
Hmmm... let me think about this some more. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
| |