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    SubjectRe: Page fault scalability patch V18: Drop first acquisition of ptl
    On Thu, 03 Mar 2005 17:30:28 +1100
    Benjamin Herrenschmidt <> wrote:

    > On Fri, 2005-03-04 at 04:19 +1100, Nick Piggin wrote:
    > > You don't want to do that for all architectures, as I said earlier.
    > > eg. i386 can concurrently set the dirty bit with the MMU (which won't
    > > honour the lock).
    > >
    > > So you then need an atomic lock, atomic pte operations, and atomic
    > > unlock where previously you had only the atomic pte operation. This is
    > > disastrous for performance.
    > Of course, but I was answering to David about sparc64 which uses
    > software TLB load :)


    The current situation on sparc64 is that the tlb miss handler is
    ~10 cycles.

    Like I said, I can use this thing if it just increases access, without
    modifying the TLB miss handler at all.

    Hmmm... let me think about this some more.
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