Messages in this thread | | | Date | Mon, 8 Sep 2003 18:07:51 +0100 | From | Jamie Lokier <> | Subject | Re: [2.4 patch] fix CONFIG_X86_L1_CACHE_SHIFT |
| |
Adrian Bunk wrote: > > Why requires? On x86, the cpu caches are fully coherent. A too small L1 > > cache shift results in false sharing on SMP, but it shouldn't cause the > > described problems. > >... > > Thanks for the correction, I falsely thought CONFIG_X86_L1_CACHE_SHIFT > does something different than it does.
Were there any changes in the kernel to do with PCI MWI settings?
(MWI == memory write and invalidate)
If MWI is set incorrectly, I think PCI DMA is capable of breaking x86 cache coherence.
-- Jamie
- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
| |