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SubjectRe: [2.4 patch] fix CONFIG_X86_L1_CACHE_SHIFT
Adrian wrote:

>With CONFIG_M686 CONFIG_X86_L1_CACHE_SHIFT was set to 5, but a Pentium 4
>requires 7.
>
>
Why requires? On x86, the cpu caches are fully coherent. A too small L1
cache shift results in false sharing on SMP, but it shouldn't cause the
described problems.

And obviously: Pentium II cpus have a 32 byte cache line, increasing the
L1 setting to 128 bytes only helps by chance.

My bet is that someone overwrites critical memory structures, and with
more padding, the critical stuff is further away.

--
Manfred


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