Messages in this thread | | | Date | Wed, 3 Sep 2003 21:37:55 +0530 (IST) | From | Nagendra Singh Tomar <> | Subject | Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this |
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Jamie, Just wondered if the store buffer is snooped in some architectures. In that case I believe the OS need not do anything for serialization (except for aliases, if they do not hit the same cache line). In x86 store buffer is not snooped which leads to all these serialization issues (other CPUs looking at stale value of data which is in the store buffer of some other CPU). Pl correct me if I have got anything wrong/
Thanx, tomar
On Wed, 3 Sep 2003, Jamie Lokier wrote:
> Geert Uytterhoeven wrote: > > > BTW the 020/030 caches are VIVT (and also only writethrough), the > 040/060 > > > caches are PIPT. > > > > That explains a bit. But the '060 stores are coherent, while the '040 > stores > > aren't. > > The L1 cache is coherent on the '040 according to the results. It's > the store buffer snooping which fails. Presumably the CPU core is > looking ahead at recent writes comparing just virtual addresses. > > -- Jamie > - > To unsubscribe from this list: send the line "unsubscribe linux-kernel" > in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ >
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