Messages in this thread | | | Date | Wed, 3 Sep 2003 14:36:34 +0200 (MEST) | From | Geert Uytterhoeven <> | Subject | Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this |
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On Wed, 3 Sep 2003, Roman Zippel wrote: > On Wed, 3 Sep 2003, Geert Uytterhoeven wrote: > > > Does the 68020 even _have_ the equivalent of a store buffer? > > > > Good question :-) > > > > After I sent the previous mail, I realized the '030 has 256 bytes I cache and > > 256 bytes D cache, while the '020 has 256 bytes I cache only. > > BTW the 020/030 caches are VIVT (and also only writethrough), the 040/060 > caches are PIPT.
That explains a bit. But the '060 stores are coherent, while the '040 stores aren't.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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