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    SubjectRe: PDC20268 UDMA troubles

    Thank you for the reply.

    I was wondering if both controllers (PDC20268 and PDC20267) should show up
    when I cat /proc/ide/pdc202xx ?

    I'm not disabling the BURST_BIT, I think the driver is, but only on the
    second card. Thus, I can't get udma5 on all 4 chains.

    This is from dmesg:

    PDC20267: IDE controller on PCI bus 00 dev 40
    PDC20267: chipset revision 2
    PDC20267: not 100% native mode: will probe irqs later
    PDC20267: (U)DMA Burst Bit ENABLED Primary PCI Mode Secondary PCI Mode.
    ide2: BM-DMA at 0x1080-0x1087, BIOS settings: hde:DMA, hdf:pio
    ide3: BM-DMA at 0x1088-0x108f, BIOS settings: hdg:DMA, hdh:pio
    PDC20268: IDE controller on PCI bus 00 dev 50
    PDC20268: chipset revision 2
    PDC20268: not 100% native mode: will probe irqs later
    PDC20268: (U)DMA Burst Bit DISABLED Primary MASTER Mode Secondary MASTER
    ide4: BM-DMA at 0x10d0-0x10d7, BIOS settings: hdi:pio, hdj:pio
    ide5: BM-DMA at 0x10d8-0x10df, BIOS settings: hdk:pio, hdl:pio

    Let me know if you need more information.


    Sean J. Swallow
    pgp (6.5.2) keyfile @

    On Thu, 4 Oct 2001 wrote:

    > There is nothing wrong with the procfs.
    > The HOST performs a sense mode on the contents of the taskfile registers
    > when loading a setfeature to change the transfer rate. Mode 5 is the
    > same
    > timings as Mode 4; however, the internal base clocks are different.
    > Also why are we disabling the BUSRT BIT?

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