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SubjectRe: Intel Xpress Server - IO APIC trouble - Kernel panic: IO APIC + timer doesn't work!
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Could you try the following patches (they will apply cleanly against 2.2.8, 
2.2.9 or 2.2.10).

I don't promis they will work, since they were written to get the NCR eagle
(EISA SMP box) to work, but the eagle is remarkably similar to the Intel
Xpress (I think we may even have licensed the motherboard design and only made
some minor tweaks).

James Bottomley

Index: linux/2.2/arch/i386/kernel/io_apic.c
diff -c linux/2.2/arch/i386/kernel/io_apic.c:1.1.1.3 linux/2.2/arch/i386/kernel/io_apic.c:1.1.1.3.2.1
*** linux/2.2/arch/i386/kernel/io_apic.c:1.1.1.3 Wed May 12 09:55:26 1999
--- linux/2.2/arch/i386/kernel/io_apic.c Wed May 12 16:45:12 1999
***************
*** 583,589 ****
--- 590,603 ----
{
struct IO_APIC_route_entry entry;
int pin, idx, bus, irq, first_notcon = 1;
+ struct IO_APIC_reg_01 reg_01;
+ int ioapic_physical_only;

+ /* James.Bottomley@ColumbiaSC.ncr.com: support for ancient
+ * IO-APIC in NCR3416. This doesn't route IRQs properly in
+ * logical mode */
+ *(int *)&reg_01 = io_apic_read(1);
+ ioapic_physical_only = (reg_01.version == 1);
printk("init IO_APIC IRQs\n");

for (pin = 0; pin < nr_ioapic_registers; pin++) {
***************
*** 594,602 ****
memset(&entry,0,sizeof(entry));

entry.delivery_mode = dest_LowestPrio;
! entry.dest_mode = 1; /* logical delivery */
entry.mask = 0; /* enable IRQ */
- entry.dest.logical.logical_dest = 0; /* but no route */

idx = find_irq_entry(pin,mp_INT);
if (idx == -1) {
--- 608,622 ----
memset(&entry,0,sizeof(entry));

entry.delivery_mode = dest_LowestPrio;
! if(ioapic_physical_only) {
! entry.dest_mode = 0; /* physical mode */
! entry.dest.physical.physical_dest = 0;
! }
! else {
! entry.dest_mode = 1; /* logical delivery */
! entry.dest.logical.logical_dest = 0;/* but no route */
! }
entry.mask = 0; /* enable IRQ */

idx = find_irq_entry(pin,mp_INT);
if (idx == -1) {
***************
*** 710,719 ****
printk("....... [IO-APIC cannot route PCI PIRQ 0-3]\n");

printk("....... : IO APIC version: %04X\n", reg_01.version);
! if ( (reg_01.version != 0x10) && /* oldest IO-APICs */
(reg_01.version != 0x11) && /* Pentium/Pro IO-APICs */
(reg_01.version != 0x13) /* Xeon IO-APICs */
)
UNEXPECTED_IO_APIC();
if (reg_01.__reserved_1 || reg_01.__reserved_2)
UNEXPECTED_IO_APIC();
--- 730,746 ----
printk("....... [IO-APIC cannot route PCI PIRQ 0-3]\n");

printk("....... : IO APIC version: %04X\n", reg_01.version);
! if(reg_01.version == 1) {
! /* ancient EISA eagle IO-APIC; doesn't support
! * logical delivery mode correctly
! */
! printk("....... : NCR 3416 IO-APIC; physical delivery only mode\n");
! }
! else if ( (reg_01.version != 0x10) && /* oldest IO-APICs */
(reg_01.version != 0x11) && /* Pentium/Pro IO-APICs */
(reg_01.version != 0x13) /* Xeon IO-APICs */
)
+
UNEXPECTED_IO_APIC();
if (reg_01.__reserved_1 || reg_01.__reserved_2)
UNEXPECTED_IO_APIC();
***************
*** 939,944 ****
--- 966,972 ----
switch (mpc_default_type)
{
case 2:
+ mp_irqs[0].mpc_irqtype = mp_ExtINT;
break;
default:
/*
Index: linux/2.2/arch/i386/kernel/smp.c
diff -c linux/2.2/arch/i386/kernel/smp.c:1.1.1.5 linux/2.2/arch/i386/kernel/smp.c:1.1.1.5.2.1
*** linux/2.2/arch/i386/kernel/smp.c:1.1.1.5 Wed May 12 09:55:24 1999
--- linux/2.2/arch/i386/kernel/smp.c Wed May 12 16:45:13 1999
***************
*** 97,102 ****
--- 97,104 ----
static void cache_APIC_registers (void);
static void stop_this_cpu (void);

+ static unsigned int external_82489DX = 0; /* set if external local apic */
+
static int smp_b_stepping = 0; /* Set if we find a B stepping CPU */

static int max_cpus = -1; /* Setup configured maximum number of CPUs to activate */
***************
*** 1233,1239 ****
printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
}

- #ifdef SMP_DEBUG
{
int reg;

--- 1235,1240 ----
***************
*** 1245,1250 ****
--- 1246,1262 ----
*/

reg = apic_read(APIC_VERSION);
+ /* James.Bottomley@ColumbiaSC.ncr.com:
+ *
+ * Support the NCR3416. However this should also work
+ * for almost all 486 SMP systems. */
+ external_82489DX = ((reg & 0xf0) == 0);
+
+ if(external_82489DX) {
+ printk("Local APIC is external 82489DX\n");
+ }
+
+ #ifdef SMP_DEBUG
SMP_PRINTK(("Getting VERSION: %x\n", reg));

apic_write(APIC_VERSION, 0);
***************
*** 1268,1275 ****

reg = apic_read(APIC_LVT1);
SMP_PRINTK(("Getting LVT1: %x\n", reg));
- }
#endif

enable_local_APIC();

--- 1280,1287 ----

reg = apic_read(APIC_LVT1);
SMP_PRINTK(("Getting LVT1: %x\n", reg));
#endif
+ }

enable_local_APIC();

***************
*** 1951,1964 ****
apic_write(APIC_LVTT , lvtt1_value);

/*
! * Divide PICLK by 16
! */
tmp_value = apic_read(APIC_TDCR);
apic_write(APIC_TDCR , (tmp_value & ~APIC_TDR_DIV_1 )
| APIC_TDR_DIV_16);

tmp_value = apic_read(APIC_TMICT);
! apic_write(APIC_TMICT, clocks/APIC_DIVISOR);
}

void __init wait_8254_wraparound(void)
--- 1963,1981 ----
apic_write(APIC_LVTT , lvtt1_value);

/*
! * Divide PICLK by 16;
! *
! * James.Bottomley@ColumbiaSC.ncr.com: this won't work for
! * external local APIC, so adjust the APIC_DIVISOR accordingly */
tmp_value = apic_read(APIC_TDCR);
apic_write(APIC_TDCR , (tmp_value & ~APIC_TDR_DIV_1 )
| APIC_TDR_DIV_16);

tmp_value = apic_read(APIC_TMICT);
! if(!external_82489DX) {
! clocks /= APIC_DIVISOR;
! }
! apic_write(APIC_TMICT, clocks);
}

void __init wait_8254_wraparound(void)
***************
*** 2043,2049 ****
* underflown to be exact, as the timer counts down ;)
*/

! calibration_result = (tt1-tt2)*APIC_DIVISOR/LOOPS;

SMP_PRINTK(("\n..... %ld CPU clocks in 1 timer chip tick.",
(unsigned long)(t2-t1)/LOOPS));
--- 2060,2069 ----
* underflown to be exact, as the timer counts down ;)
*/

! calibration_result = (tt1-tt2)/LOOPS;
! if(!external_82489DX) {
! calibration_result *= APIC_DIVISOR;
! }

SMP_PRINTK(("\n..... %ld CPU clocks in 1 timer chip tick.",
(unsigned long)(t2-t1)/LOOPS));
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