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SubjectRe: PCI problems with multiple cpu bus - 2.1.110.
Hello,

Can you try this patch? It should hopefully fix scanning of peer bridges
on all multi-bus motherboards known to me.

Have a nice fortnight
--
Martin `MJ' Mares <mj@ucw.cz> http://atrey.karlin.mff.cuni.cz/~mj/
Faculty of Math and Physics, Charles University, Prague, Czech Rep., Earth
"We all live in a yellow subroutine."


--- arch/i386/kernel/bios32.c.mj Thu Jul 23 11:28:11 1998
+++ arch/i386/kernel/bios32.c Thu Jul 23 12:02:22 1998
@@ -913,29 +913,34 @@
* Although several sources claim that the host bridges should have
* header type 1 and be assigned a bus number as for PCI2PCI bridges,
* the reality doesn't pass this test and the bus number is usually
- * hard-wired to 1.
+ * set by BIOS to the first free value.
*/
__initfunc(void pcibios_fixup_peer_bridges(void))
{
- struct pci_dev *dev;
- int cnt = 0;
+ struct pci_bus *b = &pci_root;
+ int i;

- for(dev=pci_root.devices; dev; dev=dev->sibling)
- if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
- DBG("PCI: Host bridge at %02x\n", dev->devfn);
- if (cnt) {
- struct pci_bus *b = kmalloc(sizeof(struct pci_bus), GFP_KERNEL);
+ do {
+ int n = b->number+1;
+ u16 l;
+ for(i=0; i<256; i += 8)
+ if (!pcibios_read_config_word(n, i, PCI_VENDOR_ID, &l) &&
+ l != 0x0000 && l != 0xffff &&
+ !pcibios_read_config_word(n, i, PCI_CLASS_DEVICE, &l) &&
+ l == PCI_CLASS_BRIDGE_HOST) {
+ DBG("PCI: Peer host bridge at %02x:%02x\n", n, i);
+ b = kmalloc(sizeof(*b), GFP_KERNEL);
memset(b, 0, sizeof(*b));
b->parent = &pci_root;
b->next = pci_root.next;
pci_root.next = b;
- b->self = dev;
- b->number = b->secondary = cnt;
+ b->number = b->secondary = n;
b->subordinate = 0xff;
b->subordinate = pci_scan_bus(b);
+ b->self = pci_find_slot(b, i);
+ break;
}
- cnt++;
- }
+ } while (i < 256);
}

/*
-
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