Messages in this thread | | | Date | Mon, 20 Jul 1998 10:35:38 +1200 | From | Chris Wedgwood <> | Subject | Re: patch to trim page table cache |
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On Sun, Jul 19, 1998 at 04:23:46AM +0200, Ove Ewerlid wrote:
> Please consider adding the ability to optionally disable global IPI > delivery for locked CPU's. A CPU, running hard realtime algorithms that > fit in L1, may not need these.
Good point. Is anyone actually doing anything cute along these lines, real time signal processing perhaps?
> Thus, only invalidate the TLB when the CPU is exiting from the locked > mode.
If some kind of TLB invalidation is required while the CPU is locked, when it exists, the entire TLB will have to be dumped, keeping track only of the pages which have changed would be too expensive?
-cw
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