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SubjectRe: [patch] entry.S asm improvement (removed some ugly jmp)

The processor has an internal stack of return addresses from CALL
instructions. This stack holds upto 4 addresses, and is used to predict
the destination address of a RET so that instruction prefetch can happen
earlier. If the prediction misses, then the penalty is about a dozen
cycles on a Pentium Pro, Pentium II, Celeron, Xeon, or any Intel x86
processor with "dynamic execution". The penalty on a Pentium is about
five cycles. Thus, the penalty is about the same as a pipeline flush, and
on a dynamic execution processor it is also about the same as a cache
miss. The first mis-predicted RET could cause all RETs then in the
internal stack to be mis-predicted (the easy implementation). So, be
careful in high-frequency areas. But if there will be a context switch,
or if the depth is now only 1, or will exceed 4 before the RET, then
definitely do use the PUSHL+JMP instead of CALL+JMP.

--
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jreiser@teleport.com (John Reiser)
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